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8-bit, high bandwidth multiplying dac with serial interface ad5425 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features 2.5 v to 5.5 v supply operation 50 mhz serial interface 9.5 msps update rate inl of 0.25 lsb 10 mhz multiplying bandwidth 10 v reference input low glitch energy: <2 nv-s extended temperature range: ?40c to +125c 10-lead msop package guaranteed monotonic 4-quadrant multiplication power-on reset with brownout detection ldac function 0.4 a typical power consumption applications portable battery-powered applications waveform generators analog processing instrumentation applications programmable amplifiers and attenuators digitally controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming general description the ad5425 1 is a cmos, 8-bit, current output digital-to- analog converter that operates from a 2.5 v to 5.5 v power supply, making it suitable for battery-powered applications and many other applications. this dac utilizes a double buffered, 3-wire serial interface that is compatible with spi ? , qspi ? , microwire ? , and most dsp interface standards. an ldac pin is also provided, which allows simultaneous updates in a multi-dac configuration. on power-up, the internal shift register and latches are filled with 0s and the dac outputs are 0 v. as a result of manufacturing on a cmos submicron process, this dac offers excellent 4-quadrant multiplication charac- teristics with large signal multiplying bandwidths of 10 mhz. the applied external reference input voltage (v ref ) determines the full-scale output current. an integrated feedback resistor, r fb , provides temperature tracking and full-scale voltage output when combined with an external i-to-v precision amplifier. the ad5425 is available in a small, 10-lead msop package. 1 u.s. patent no. 5,969,657 functional block diagram sclk sync ad5425 v ref i out 2 i out 1 r fb r 8-bit r-2r dac dac register sdin v dd gnd power-on reset ldac control logic and input shift register input latch 03161-001 figure 1.
ad5425 rev. a | page 2 of 28 table of contents specifications ..................................................................................... 3 timing characteristics ..................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 ter mi nolo g y .................................................................................... 13 theory of operation ...................................................................... 14 circuit operation ....................................................................... 14 single-supply applications ....................................................... 16 positive output voltage ............................................................. 16 adding gain ................................................................................ 17 dacs used as a divider or programmable gain element ... 17 reference selection .................................................................... 17 amplifier selection .................................................................... 18 serial interface ............................................................................ 19 microprocessor interfacing ....................................................... 19 pcb layout and power supply decoupling ................................ 22 evaluation board ........................................................................ 22 operating the evaluation board .............................................. 22 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 3/05rev. 0 to rev. a updated format................................................................ universal changes to specifications section.................................................3 added figure 18, figure 20, figure 21........................................10 change to table 7 ..........................................................................18 2/04revision 0: initial version
ad5425 rev. a | page 3 of 28 specifications v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v. temperature range for y version: ?40c to +125c. all specifications t min to t max , unless otherwise noted. dc performance measured with op177, ac performance with ad8038, unless otherwise noted. table 1. parameter min typ max unit conditions/comments static performance resolution 8 bits relative accuracy 0.25 lsb differential nonlinearity 0.5 lsb guaranteed monotonic gain error 10 mv gain error temperature coefficient 5 ppm fsr/c output leakage current 10 na data = 0x0000, t a = 25c, i out 1 20 na data = 0x0000, t = ?40c to +125c, i out 1 reference input 1 reference input range 10 v v ref input resistance 8 10 12 k input resistance tc = ?50 ppm/c r fb resistance 8 10 12 k input resistance tc = ?50 ppm/c input capacitance code zero scale 3 6 pf code full scale 5 8 pf digital input/output 1 input high voltage, v ih 1.7 v input low voltage, v il 0.6 v output high voltage, v oh v dd ? 1 v v dd = 4.5 v to 5 v, i source = 200 a v dd ? 0.5 v v dd = 2.5 v to 3.6 v, i source = 200 a output low voltage, v ol 0.4 v v dd = 4.5 v to 5 v, i sink = 200 a 0.4 v v dd = 2.5 v to 3.6 v, i sink = 200 a input leakage current, i il 1 a input capacitance 4 10 pf dynamic performance 1 reference multiplying bandwidth 10 mhz v ref = 3.5 v, dac loaded all 1s output voltage settling time v ref = 3.5 v, r load = 100 , dac latch alternately loaded with 0s and 1s measured to 1 mv 90 160 ns measured to 4 mv 55 110 ns measured to 16 mv 50 100 ns digital delay 40 75 ns interface delay time 10% to 90% settling time 15 30 ns rise and fall time, v ref = 10 v, r load = 100 digital-to-analog glitch impulse 2 nv-s 1 lsb change around major carry v ref = 0 v multiplying feedthrough error dac latch loaded with all 0s. v ref = 3.5 v 70 db 1 mhz 48 db 10 mhz output capacitance i out 1 12 17 pf all 0s loaded 25 30 pf all 1s loaded i out 2 22 25 pf all 0s loaded 10 12 pf all 1s loaded digital feedthrough 0.1 nv-s feedthrough to dac output with sync high and alternate loading of all 0s and all 1s analog thd 81 db v ref = 3.5 v p-p; all 1s loaded, f = 1 khz
ad5425 rev. a | page 4 of 28 parameter min typ max unit conditions/comments digital thd clock = 1 mhz, v ref = 3.5 v, c comp = 1.8 pf 50 khz f out 70 db 20 khz f out 73 db output noise spectral density 25 nv hz @ 1 khz sfdr performance (wide band) clock = 2 mhz , v ref = 3.5 v 50 khz f out 67 db 20 khz f out 68 db sfdr performance (narrow band) clock = 2 mhz, v ref = 3.5 v 50 khz f out 73 db 20 khz f out 75 db intermodulation distortion 79 db f 1 = 20 khz, f 2 = 25 khz, clock = 2 mhz, v ref = 3.5 v power requirements power supply range 2.5 5.5 v i dd 0.6 a t a = 25c, logic inputs = 0 v or v dd 0.4 5 a logic inputs = 0 v or v dd , t = ?40c to +125c power supply sensitivity 0.001 %/% v dd = 5% 1 guaranteed by design and characterization, not subject to production test.
ad5425 rev. a | page 5 of 28 timing characteristics all input signals are specified with tr = tf = 1 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. v dd =2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v, temperature range for y version: ?40c to +125c ; all specifications t min to t max , unless otherwise noted. table 2. parameter 1 v dd = 2.5 v to 5.5 v unit conditions/comments f sclk 50 mhz max maximum clock frequency t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 2 13 ns min sync falling edge to sclk falling edge setup time t 5 5 ns min data setup time t 6 3 ns min data hold time t 7 5 ns min sync rising edge to sclk falling edge t 8 30 ns min minimum sync high time t 9 0 ns min sclk falling edge to ldac falling edge t 10 12 ns min ldac pulse width t 11 10 ns min sclk falling edge to ldac rising edge 1 guaranteed by design and characterization, not subject to production test. 2 falling or rising edge as determined by control bits of serial word. t 8 sclk sync din ldac 2 ldac 1 db7 t 4 db0 notes: 1 asynchronous ldac update mode. 2 synchronous ldac update mode. t 11 t 10 t 1 t 9 t 5 t 6 t 2 t 3 t 7 03161-002 figure 2. timing diagram
ad5425 rev. a | page 6 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd ?0.3 v to +7 v v ref , r fb to gnd ?12 v to +12 v i out 1, i out 2 to gnd ?0.3 v to v dd + 0.3 v logic input and output 1 ?0.3 v to v dd + 0.3 v operating temperature range extended industrial (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 10-lead msop ja thermal impedance 206c/w lead temperature, soldering (10 secs) 300c ir reflow, peak temperature (<20 secs) 235c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 1 overvoltages at sclk, sync , din, and ldac are clamped by internal diodes. current should be limited to the maximum ratings given. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without de tection. although th is product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5425 rev. a | page 7 of 28 pin configuration and fu nction descriptions i out 1 1 i out 2 2 gnd 3 sclk 4 sdin 5 r fb 10 v ref 9 v dd 8 ldac 7 sync 6 ad5425 top view (not to scale) 03161-003 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic function 1 i out 1 dac current output. 2 i out 2 dac analog ground. this pin should normally be tied to the analog ground of the system. 3 gnd digital ground pin. 4 sclk serial clock input. data is clocked into the input shift register on each falling edge of the serial clock input. this device can accommodate clock rates of up to 50 mhz. 5 sdin serial data input. data is cloc ked into the 8-bit input register on each falling edge of the serial clock input. 6 sync active low control input. this is the frame synchronization signal fo r the input data. when sync goes low, it powers on the sclk and din buffers and the input shift register is enabled. data is tr ansferred on each falling edge of the following 8 clocks. 7 ldac load dac input. updates the dac output. the dac is updated when this signal goes low or alternatively; if this line is held permanently low, an auto matic update mode is selected whereby the dac is updated after 8 sclk falling edges with sync low. 8 v dd positive power supply input. this part can be operated from a supply of 2.5 v to 5.5 v. 9 v ref dac reference voltage input terminal. 10 r fb dac feedback resistor pin. establ ishes voltage output for the dac by conne cting to external amplifier output.
ad5425 rev. a | page 8 of 28 typical performance characteristics 03161-004 code 250 0 50 100 150 200 inl (lsb) 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 t a = 25c v ref = 10v v dd = 5v figure 4. inl vs. code (8-bit dac) 03161-005 code 250 0 50 100 150 200 inl (lsb) 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.15 ?0.20 t a = 25c v ref = 10v v dd = 5v figure 5. dnl vs. code (8-bit dac) xxxxx-xxx reference voltage 10 23456789 inl (lsb) 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 t a = 25c v dd = 5v max inl min inl figure 6. inl vs. reference voltage xxxxx-xxx reference voltage 10 23456789 dnl (lsb) 0.4 0.2 0 ?0.2 ?0.4 ?0.6 t a = 25c v dd = 5v min dnl max dnl figure 7. dnl vs. reference voltage 03161-008 temperature (c) 120 ?40 ?20 0 20 40 60 80 100 i out leakage (na) 1.6 1.2 1.4 0.8 1.0 0.4 0.2 0.6 0 i out 1 v dd 5v i out 1 v dd 3v figure 8. i out 1 leakage current vs. temperature 03161-009 temperature (c) 140 ?60 ?40 ?20 0 20 40 60 80 100 120 error (mv) 5 3 2 4 1 0 ?1 ?2 ?3 ?4 ?5 v dd = 5v v dd = 2.5v v ref = 10v figure 9. gain error vs. temperature
ad5425 rev. a | page 9 of 28 03161-010 v bias (v) 1.5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 lsbs 0.5 0.3 0.1 ?0.1 ?0.3 ?0.5 max inl min inl max dnl min dnl t a = 25c v dd = 3v v ref = 0v figure 10. linearity vs. v bias voltage applied to i out 2 03161-011 v bias (v) 1.5 0.5 1.0 voltage (mv) 1.4 0.8 1.0 1.2 0.4 0.6 0 0.2 ?0.2 ?0.4 gain error offset error t a = 25c v dd = 3v v ref = 0v figure 11. gain and offset errors vs. v bias voltage applied to i out 2 03161-012 v bias (v) 2.5 0.5 1.0 1.5 2.0 lsbs 0.5 0.3 ?0.1 0.1 ?0.3 ?0.5 max inl min inl max dnl min dnl v dd = 5v v ref = 0v figure 12. linearity vs. v bias voltage applied to i out 2 03161-013 v bias (v) 2.5 0.5 1.0 1.5 2.0 voltage (mv) 2.5 2.0 1.5 1.0 0.5 0 ?0.5 gain error offset error v dd = 5v v ref = 0v figure 13. gain and offset errors vs. voltage applied to i out 2 03161-014 v bias (v) 2.5 0 0.5 1.0 1.5 2.0 voltage (mv) 10.0 6.0 8.0 2.0 4.0 ?2.0 0 ?4.0 gain error offset error t a = 25c v dd = 5v v ref = 2.5v figure 14. gain and offset errors vs. v bias voltage applied to i out 2 03161-015 v bias (v) 2.0 0 0.5 1.0 1.5 lsbs 1.0 0.4 0.6 0.8 0 0.2 ?0.6 ?0.4 ?0.2 ?0.8 ?1.0 max inl bias min inl bias t a = 25c v dd = 5v v ref = 2.5v max dnl bias min dnl bias figure 15. linearity vs. v bias voltage applied to i out 2
ad5425 rev. a | page 10 of 28 03161-016 input voltage (v) 5 01234 current (ma) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 v dd = 3v v dd = 2.5v v dd = 5v t a = 25c figure 16. supply current vs. input voltage 03161-017 voltage (v) 5.5 2.5 3.0 3.5 4.0 4.5 5.0 threshold voltage (v) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 t a = 25c v il v ih figure 17. threshold voltages vs. supply voltage 03161-018 frequency (hz) 100m 1 10 100 1k 10k 100k 1m 10m gain (db) 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf ad8083 amplifier figure 18. reference multiplying bandwidthall 1s loaded 03161-019 time (ns) 300 0 50 100 150 200 250 output voltage (v) 0.060 0.030 0.040 0.050 0.010 0.020 ?0.010 0 ?0.020 t a = 25c v ref = 0v ad8038 amplifier c comp = 1.8pf v dd 3v, 0v ref nrg = 0.088nvs 0x800 to 0x7ff v dd 5v, 0v ref nrg = 0.119nvs, 0x800 to 0x7ff v dd 3v, 0v ref nrg = 1.877nvs 0x7ff to 0x800 v dd 5v, 0v ref nrg = 2.049nvs 07xff to 0x800 figure 19. midscale transition, v ref = 3.5 v 03161-020 frequency (hz) 100m 1 10 100 1k 10k 100k 1m 10m gain (db) 6 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 ?66 ?72 ?78 ?84 ?90 ?96 ?102 t a = 25c loading zs to fs all on db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 all off t a = 25c v dd = 5v v ref = 3.5v input c comp = 1.8pf ad8083 amplifier figure 20. reference multiplying bandwidth vs. frequency and code 03161-021 frequency (hz) 100m 10k 100k 1m 10m gain (db) 3 0 ?3 ?6 ?9 t a = 25c v dd = 5v ad8038 amplifier v ref = 2v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1.47pf v ref = 3.51v, ad8038 c c 1.8pf v ref = 2v, ad8038 c c 1.47pf figure 21. reference multiplying bandwidth vs. frequency and compensation capacitor
ad5425 rev. a | page 11 of 28 03161-022 frequency (hz) 1m 1 10 100 1k 10k 100k thd + n (db) ?60 ?75 ?70 ?65 ?80 ?85 ?90 t a = 25c v dd = 3v v ref = 3.5v p-p figure 22. thd and noise vs. frequency 03161-023 frequency (hz) 10m 1 10 100 1k 10k 100k 1m power supply rejection 20 ?20 0 ?60 ?40 ?100 ?80 ?120 v dd = 3v amplifier = ad8038 full scale zero scale figure 23. power supply rejection vs. frequency 03161-024 frequency (hz) 1m 0 200k 400k 600k 800k sfdr (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 t a = 25c v dd = 5v v ref = 3.5v ad8038 amplifier figure 24. wideband sfdr, clock = 2 mhz, f out = 50 khz 03161-025 frequency (hz) 1m 0 200k 400k 600k 800k sfdr (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 t a = 25c v dd = 5v v ref = 3.5v ad8038 amplifier figure 25. wideband sfdr, clock = 2 mhz, f out = 20 khz 03161-026 frequency (hz) 30k 10k 14k12k 18k 22k 26k 16k 20k 24k 28k sfdr (db) 0 ?40 ?30 ?20 ?10 ?60 ?50 ?100 ?90 ?80 ?70 ?110 t a = 25c v dd = 5v v ref = 3.5v ad8038 amplifier figure 26. narrowband sfdr, clock = 2 mhz, f out = 20 khz 03161-027 frequency (hz) 75k 25k 35k30k 45k 55k 65k 40k 50k 60k 70k sfdr (db) 0 ?30 ?20 ?10 ?60 ?50 ?40 ?100 ?90 ?80 ?70 ?110 t a = 25c v dd = 5v v ref = 3.5v ad8038 amplifier figure 27. narrowband sfdr, clock = 2 mhz, f out = 50 khz
ad5425 rev. a | page 12 of 28 03161-028 frequency (hz) 35k 10k 15k 20k 25k 30k imd (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 v dd = 5v v ref = 3.5v ad8038 amplifier figure 28. narrowband imd (50%) clock = 2 mhz, f out 1 = 20 khz, f out 2 = 25 khz
ad5425 rev. a | page 13 of 28 terminology relative accuracy relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero and full scale and is normally expressed in lsbs or as a percentage of full-scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of ?1 lsb maximum over the operating temperature range ensures monotonicity. gain error gain error or full-scale error is a measure of the output error between an ideal dac and the actual device output. for these dacs, ideal maximum output is v ref ? 1 lsb. gain error of the dacs is adjustable to 0 with external resistance. output leakage current output leakage current is current that flows in the dac ladder switches when these are turned off. for the i out 1 terminal, it can be measured by loading all 0s to the dac and measuring the i out 1 current. minimum current flows in the i out 2 line when the dac is loaded with all 1s. output capacitance capacitance from i out 1 or i out 2 to agnd. output current settling time this is the amount of time it takes for the output to settle to a specified level for a full-scale input change. for these devices, it is specified with a 100 resistor to ground. the settling time specification includes the digital delay from sync rising edge to the full-scale output charge. digital-to-analog glitch impulse the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is normally specified as the area of the glitch in either pa-s or nv-s depending upon whether the glitch is measured as a current or voltage signal. digital feedthrough when the device is not selected, high frequency logic activity on the device digital inputs can be capacitively coupled to show up as noise on the i out pins and subsequently into the following circuitry. this noise is digital feedthrough. multiplying feedthrough error this is the error due to capacitive feedthrough from the dac reference input to the dac i out 1 terminal, when all 0s are loaded to the dac. total harmonic distortion (thd) the dac is driven by an ac reference. the ratio of the rms sum of the harmonics of the dac output to the fundamental value is the thd. usually only the lower order harmonics are included, such as second to fifth. ( ) 1 2 5 2 4 2 3 2 2 log20 v vvvv thd +++ = digital intermodulation distortion second-order intermodulation distortion (imd) measurements are the relative magnitude of the fa and fb tones generated digitally by the dac and the second-order products at 2fa ? fb and 2fb ? fa. spurious-free dynamic range (sfdr) sfdr is the usable dynamic range of a dac before spurious noise interferes or distorts the fundamental signal. it is the mea- sure of the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full nyquist bandwidth (half the dac sampling rate, or f s /2). narrow band sfdr is a measure of sfdr over an arbitrary window size, in this case 50% of the fundamental. digital sfdr is a measure of the usable dynamic range of the dac when the signal is a digitally generated sine wave.
ad5425 rev. a | page 14 of 28 theory of operation the ad5425 is an 8-bit current output dac consisting of a standard inverting r-2r ladder configuration. a simplified diagram is shown in figure 29 . the feedback resistor, r fb , has a value of r. the value of r is typically 10 k (minimum 8 k and maximum 12 k). if i out 1 and i out 2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. therefore, the input resistance presented at v ref is always constant and nominally of value r. the dac output, i out , is code-dependent, producing various resistances and capacitances. when choosing the external amplifier, take into account the variation in impedance generated by the dac on the amplifiers inverting input node. v ref i out 2 dac data latches and drivers i out 1 r fb 2r s1 2r s2 2r s3 2r 2r s8 r r rr 03161-029 figure 29. simplified ladder access is provided to the v ref , r fb , i out 1, and i out 2 terminals of the dac, making the device extremely versatile and allowing it to be configured in several different operating modes, for exam- ple, to provide a unipolar output, bipolar output, or in single- supply modes of operation in unipolar mode or 4-quadrant multiplication in bipolar mode. note that a matching switch is used in series with the internal r fb feedback resistor. if users attempt to measure r fb , power must be applied to v dd to achieve continuity. circuit operation unipolar mode using a single op amp, this device can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in figure 30 . when an output amplifier is connected in unipolar mode, the output voltage is given by n ref out d vv 2 ?= where d is the fractional representation of the digital word loaded to the dac, in this case 0 to 255, and n is the number of bits. note that the output voltage polarity is opposite to the v ref polarity for dc reference voltages. this dac is designed to operate with either negative or positive reference voltages. the v dd power pin is used by only the inter- nal digital logic to drive the dac switches on and off states. this dac is also designed to accommodate ac reference input signals in the range of ?10 v to +10 v. with a fixed 10 v reference, the circuit shown in figure 30 gives a unipolar 0 v to ?10 v output voltage swing. when v in is an ac signal, the circuit performs 2-quadrant multiplication. table 5 shows the relationship between digital code and the expected output voltage for unipolar operation. table 5. unipolar code table digital input analog output (v) 1111 1111 ?v ref (255/256) 1000 0000 ?v ref (128/256) = ?v ref /2 0000 0001 ?v ref (1/256) 0000 0000 ?v ref (0/256) = 0 v out = 0 to ?v ref sclk sdin gnd v ref sync i out 2 i out 1 r fb agnd ad5425 r1 r2 a1 v ref v dd v dd c1 notes: 1. r1 and r2 used only if gain adjustment is required. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. microcontroller 03161-030 a1 figure 30. unipolar operation
ad5425 rev. a | page 15 of 28 v out =?v ref to +v ref sclk sdin gnd v ref 10v sync i out 2 i out 1 r fb agnd ad5425 r1 r2 a1 v ref v dd v dd c1 notes: 1. r1 and r2 are used only if gain adjustment is required. adjust r1 for v out = 0 v with code 10000000 loaded to dac. 2. matching and tracking is essential for resistor pairs r3 and r4. 3. c1 phase compensation (1pf to 2pf) may be required if a1/a2 is a high speed amplifier. microcontroller r4 10k r5 20k r3 20k a2 a1 03161-031 figure 31. bipolar operation (4-quadrant multiplication) bipolar operation in some applications, it may be necessary to generate full 4- quadrant multiplying operation or a bipolar output swing. this can be easily accomplished by using another external amplifier and some external resistors, as shown in figure 31 . in this circuit, the second amplifier, a2, provides a gain of 2. biasing the external amplifier with an offset from the reference voltage, results in full 4-quadrant multiplying operation. the transfer function of this circuit shows that both negative and positive output voltages are created as the input data, d, is incremented from code zero (v out = ?v ref ) to midscale (v out = 0 v ) to full scale (v out = +v ref ). () ref n ref out vdvv ? = ? 1 2/ where d is the fractional representation of the digital word loaded to the dac and n is the resolution of the dac. when v in is an ac signal, the circuit performs 4-quadrant multiplication. table 6 shows the relationship between digital code and the expected output voltage for bipolar operation. table 6. bipolar code table digital input analog output (v) 1111 1111 +v ref (127/128) 1000 0000 0 0000 0001 ?v ref (127/128) 0000 0000 ?v ref (128/128) stability in the i-to-v configuration, the i out of the dac and the inverting node of the op amp must be connected as closely as possible and proper pcb layout techniques must be employed. since every code change corresponds to a step function, gain peaking can occur if the op amp has limited gbp and there is excessive parasitic capacitance at the inverting node. this parasitic capacitance introduces a pole into the open-loop response, which can cause ringing or instability in closed-loop applications. an optional compensation capacitor, c1, can be added in parallel with r fb for stability, as shown in figure 30 and figure 31 . too small a value of c1 can produce ringing at the output, while too large a value can adversely affect the settling time. c1 should be found empirically, but 1 pf to 2 pf is generally adequate for compensation.
ad5425 rev. a | page 16 of 28 single-supply applications current mode operation in the current mode circuit of figure 32 , i out 2 and hence i out 1 is biased positive by an amount applied to v bias . in this configuration, the output voltage is given by v out = [ d ( r fb /r dac ) (v bias ? v in )] + v bias as d varies from 0 to 255, the output voltage varies from v out = v bias to v out = 2v bias ? v in v out gnd v in i out 2 i out 1 r fb a1 v ref v dd v bias v dd c1 notes: 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. a1 03161-032 figure 32. single-supply current mode operation v bias should be a low impedance source capable of sinking and sourcing all possible variations in current at the i out 2 terminal without any problems. it is important to note that v in is limited to low voltages because the switches in the dac ladder no longer have the same source- drain drive voltage. as a result, their on resistance differs and this degrades the linearity of the dac. voltage switching mode of operation figure 33 shows this dac operating in the voltage switching mode. the reference voltage v in is applied to the i out 1 pin, i out 2 is connected to agnd, and the output voltage is available at the v ref terminal. in this configuration, a positive reference voltage results in a positive output voltage, making single- supply operation possible. the output from the dac is voltage at a constant impedance (the dac ladder resistance), thus an op amp is necessary to buffer the output voltage. the reference input no longer sees constant input impedance, but one that varies with code. so, the voltage input should be driven from a low impedance source. v in r2 r1 v out gnd i out 2 i out 1 r fb a1 v ref v dd v dd notes: 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. a1 03161-033 figure 33. single-supply voltage switching mode operation it is important to note that v in is limited to low voltage because the switches in the dac ladder no longer have the same source drain drive voltage. as a result, their on resistance differs, which degrades the linearity of the dac. v in must also not go negative by more than 0.3 v, otherwise an internal diode turns on, exceeding the maximum ratings of the device. in this type of application, the full range of the dac multiplying capability is lost. positive output voltage note that the output voltage polarity is opposite to the v ref polarity for dc reference voltages. to achieve a positive voltage output, an applied negative reference to the input of the dac is preferred over the output inversion through an inverting amplifier because of the resistor tolerance errors. to generate a negative reference, the reference can be level shifted by an op amp such that the v out and gnd pins of the reference become the virtual ground and ?2.5 v respectively, as shown in figure 34 . v dd r fb i out 1 i out 2 c1 v out = 0v to +2.5v gnd v dd = 5v v ref notes: 1 additional pins omitted for clarity. 2 c1 phase compensation (1pf to 2pf) may be required, if a1 is a high speed amplifier. adr03 v out v in gnd ?5v +5v ?2.5v 04588-033 figure 34. positive voltage output with minimum of components
ad5425 rev. a | page 17 of 28 adding gain in applications where the output voltage is required to be greater than v in , gain can be added with an additional external amplifier or it can be achieved in a single stage. it is important to take into consideration the effect of temperature coefficients of the thin film resistors of the dac. simply placing a resistor in series with the r fb resistor causes mismatches in the temp- erature coefficients and results in larger gain temperature coefficient errors. instead, the circuit of figure 35 is a recom- mended method of increasing the gain of the circuit. r1, r2, and r3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the dac. this approach is recommended in circuits where gains of greater than 1 are required. r1 r3 r2 v in r1 = r2r3 r2 + r3 gain = r2 + r3 r2 notes: 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. v out gnd i out 2 i out 1 r fb a1 v ref v dd v dd c1 03161-035 figure 35. increasing the gain of current output dac dacs used as a divider or programmable gain element current steering dacs are very flexible and lend themselves to many different applications. if this type of dac is connected as the feedback element of an op amp and r fb is used as the input resistor as shown in figure 36 , then the output voltage is inversely proportional to the digital input fraction, d. for d = 1 ? 2 ?n , the output voltage is v out = ? v in / d = ? v in /(1 ? 2 ? n ) as d is reduced, the output voltage increases. for small values of d, it is important to ensure that the amplifier does not satur- ate and that the required accuracy is met. for example, an 8-bit dac driven with the binary code 0x10 (00010000), that is, 16 decimal, in the circuit of figure 36 , should cause the output voltage to be 16 v in . however, if the dac has a linearity specification of 0.5 lsb, then d can in fact have a weight anywhere in the range 15.5/256 to 16.5/256. therefore, the possible output voltage is in the range of 15.5 v in to 16.5 v in an error of 3%, even though the dac itself has a maximum error of 0.2%. gnd i out 1 r fb v ref v dd v dd note: 1. additional pins omitted for clarity. v out v in 03161-036 figure 36. current steering dac used as a divider or programmable gain element dac leakage current is also a potential error source in divider circuits. the leakage current must be counterbalanced by an opposite current supplied from the op amp through the dac. since only a fraction, d, of the current into the v ref terminal is routed to the i out 1 terminal, the output voltage has to change as follows: output error voltage due to dac leakage = (leakage r)/d where r is the dac resistance at the v ref terminal. for a dac leakage current of 10 na, r = 10 k. with a gain (that is, 1/d) of 16 the error voltage is 1.6 mv. reference selection when selecting a reference for use with the ad5425 current output dac, pay attention to the references output voltage temperature coefficient specification. this parameter not only affects the full-scale error, but can also affect the linearity (inl and dnl) performance. the reference temperature coefficient should be consistent with the system accuracy specifications. for example, an 8-bit system required to hold its overall specification to within 1 lsb over the temperature range 0c to 50c dictates that the maximum system drift with temperature should be less than 78 ppm/c. a 12-bit system with the same temperature range to overall specification within 2 lsb requires a maximum drift of 10 ppm/c. by choosing a precision reference with a low output temperature coefficient, this error source can be minimized. table 7 suggests some of the references available from analog devices that are suitable for use with this range of current output dacs.
ad5425 rev. a | page 18 of 28 amplifier selection the primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset vol- tage. the input offset voltage of an op amp is multiplied by the variable gain (due to the code dependent output resistance of the dac) of the circuit. a change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifiers input offset voltage. this output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which if large enough, could cause the dac to be nonmonotonic. the input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, r fb . most op amps have input bias currents low enough to prevent any significant errors. common-mode rejection of the op amp is important in voltage switching circuits, since it produces a code dependent error at the voltage output of the circuit. most op amps have adequate common-mode rejection for use at an 8-bit resolution. provided the dac switches are driven from true wideband low impedance sources (v in and agnd), they settle quickly. conse- quently, the slew rate and settling time of a voltage switching dac circuit is determined largely by the output op amp. to obtain minimum settling time in this configuration, it is impor- tant to minimize capacitance at the v ref node (voltage output node in this application) of the dac. this is done by using low inputs capacitance buffer amplifiers and careful board design. most single-supply circuits include ground as part of the analog signal range, which in turns requires an amplifier that can handle rail-to-rail signals. there is a large range of single-supply amplifiers available from analog devices. table 7. suitable adi precision references part no. output voltage (v) initial tolerance (%) temp drift (ppm/c) i ss (ma) output noise (v p-p) package adr01 10 0.05 3 1 20 soic-8 adr01 10 0.05 9 1 20 tsot-23, sc70 adr02 5 0.06 3 1 10 soic-8 adr02 5 0.06 9 1 10 tsot-23, sc70 adr03 2.5 0.10 3 1 6 soic-8 adr03 2.5 0.10 9 1 6 tsot-23, sc70 adr06 3 0.10 3 1 10 soic-8 adr06 3 0.10 9 1 10 tsot-23, sc70 adr431 2.5 0.04 3 0.8 3.5 soic-8 adr435 5 0.04 3 0.8 8 soic-8 adr391 2.5 0.16 9 0.12 5 tsot-23 adr395 5 0.10 9 0.12 8 tsot-23 table 8. suitable precision adi op amps part no. supply voltage (v) v os (max) (v) i b (max) (na) b 0.1 hz to 10 hz noise (v p-p) supply current (a) package op97 2 to 20 25 0.1 0.5 600 soic-8 op1177 2.5 to 15 60 2 0.4 500 msop, soic-8 ad8551 2.7 to 5 5 0.05 1 975 msop, soic-8 ad8603 1.8 to 6 50 0.001 2.3 50 tsot ad8628 2.7 to 6 5 0.1 0.5 850 tsot, soic-8 table 9. suitable high speed adi op amps part no. supply voltage (v) bw @ acl (mhz) slew rate (v/s) v os (max) (v) i b (max) (na) b package ad8065 5 to 24 145 180 1500 6000 soic-8, sot-23,msop ad8021 2.5 to 12 490 120 1000 10500 soic-8, msop ad8038 3 to 12 350 425 3000 750 soic-8, sc70-5 ad9631 3 to 6 320 1300 10000 7000 soic-8
ad5425 rev. a | page 19 of 28 serial interface the ad5425 has a simple 3-wire interface that is compatible with spi, qspi, microwire, and dsp interface standards. data is written to the device in 8-bit words. this 8-bit word consists of 8 data bits, as shown in figure 37 . db0 (lsb) db7 (msb) db7 db6 db5 db4 db3 db2 db0db1 data bits 03161-037 figure 37. 8-bit input shift register contents sync is an edge-triggered input that acts as a frame synchro- nization signal and chip enable. data can be transferred into the device only while sync is low. to start the serial data transfer, sync should be taken low, observing the minimum sync falling to sclk falling edge setup time, t 4 . after loading eight data bits to the shift register, the sync line is brought high. the contents of the dac register and the output are updated by bringing ldac low any time after the 8-bit data transfer is complete, as seen in the timing diagram of figure 2 . ldac can be tied permanently low if required. for another serial transfer to take place, the interface must be enabled by another falling edge of sync . low power serial interface to minimize the power consumption of the device, the interface fully powers up only when the device is being written to, that is, on the falling edge of sync . the sclk and sdin input buffers are powered down on the rising edge of sync . microprocessor interfacing microprocessor interfacing to this dac is via a serial bus that uses standard protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire inter- face consisting of a clock signal, a data signal, and a synchro- nization signal. an ldac pin is also included. the ad5425 requires an 8-bit word with the default being data valid on the falling edge of sclk, but this is changeable via the control bits in the data-word. adsp-21xx-to ad5425 interface the adsp-21xx family of dsps is easily interfaced to this family of dacs without extra glue logic. figure 38 shows an example of an spi interface between the dac and the adsp- 2191. sck of the dsp drives the serial data line, din. sync is driven from one of the port lines, in this case spixsel . sclk sck ad5425 1 spixsel sdin mosi adsp-2191 1 03161-038 1 additional pins omitted for clarity. sync figure 38. adsp-2191 spi-to-ad5425 interface a serial interface between the dac and dsp sport is shown in figure 39 . in this interface example, sport0 is used to transfer data to the dac shift register. transmission is initiated by writing a word to the tx register after the sport has been enabled. in a write sequence, data is clocked out on each rising edge of the dsps serial clock and clocked into the dac input shift register on the falling edge of its sclk. the update of the dac output takes place on the rising edge of the sync signal. 03161-039 sclk sclk ad5425 1 sync tfs sdin dt adsp-2101/ adsp-2103/ adsp-2191 1 1 additional pins omitted for clarity. figure 39. adsp-2101/adsp-2103/adsp-2191 sport-to-ad5425 interface communication between two devices at a given clock speed is possible when the following specifications from one device to the other are compatible: frame sync delay and frame sync setup and hold, data delay and data setup and hold, and sclk width. the dac interface expects a t 4 (sync falling edge to sclk falling edge setup time) of 13 ns minimum. consult the adsp- 21xx user manual for information on clock and frame sync frequencies for the sport register. table 10. sport control register setup name setting description tfsw 1 alternate framing invtfs 1 active low frame signal dtype 00 right-justify data isclk 1 internal serial clock tfsr 1 frame every word itfs 1 internal framing signal slen 0111 8-bit data-word
ad5425 rev. a | page 20 of 28 adsp-bf5xx-to-ad5425 interface the adsp-bf5xx family of processors has an spi-compatible port that enables the processor to communicate with spi- compatible devices. a serial interface between the adsp-bf5xx and the ad5425 dac is shown in figure 40 . in this configura- tion, data is transferred through the mosi (master output/slave input) pin. sync is driven by the spi chip select pin, which is a reconfigured programmable flag pin. 03161-040 sclk sck ad5425 1 sync spixsel sdin mosi adsp-bf5xx 1 1 additional pins omitted for clarity. figure 40. adsp-bf5xx-to-ad5425 interface the adsp-bf5xx processor incorporates channel synchronous serial ports (sport). a serial interface between the dac and the dsp sport is shown in figure 41 . when the sport is enabled, initiate transmission by writing a word to the tx register. the data is clocked out on each rising edge of the dsps serial clock and clocked into the dacs input shift register on the falling edge of its sclk. the dac output is updated by using the transmit frame synchronization (tfs) line to provide a sync signal. 03161-041 sclk sclk ad5425 1 sync tfs sdin dt adsp-bf5xx 1 1 additional pins omitted for clarity. figure 41. adsp-bf5xx-to-ad5425 interface 80c51/80l51-to-ad5425 interface a serial interface between the dac and the 8051 is shown in figure 42 . txd of the 8051 drives sclk of the dac serial interface, while rxd drives the serial data line, d in . p3.3 is a bit- programmable pin on the serial port that drives sync . when data is transmitted to the switch, p3.3 is taken low. the 80c51/ 80l51 transmits data in 8-bit bytes, which fits the ad5425 since it only requires an 8-bit word. data on rxd is clocked out of the microcontroller on the rising edge of txd and is valid on the falling edge. as a result, no glue logic is required between the dac and microcontroller interface. p3.3 is taken high at the completion of this cycle. the 8051 provides the lsb of its sbuf register as the first bit in the data stream. the dac input reg- ister requires that the msb is the first bit received. the transmit routine should take this into account. 03161-042 sync p1.1 ad5425 1 sclk txd sdin rxd 8051 1 1 additional pins omitted for clarity. figure 42. 80c51/80l51-to-ad5425 interface mc68hc11 interface- to-ad5425 interface figure 43 shows an example of a serial interface between the dac and the mc68hc11 microcontroller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1), clock polarity bit (cpol) = 0, and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr) (see the mc68hc11 user manual). sck of the mc68hc11 drives the sclk of the dac interface, the mosi output drives the serial data line, d in , of the ad5425. the sync signal is derived from a port line, pc7. when data is being transmitted to the ad5425, the sync line is taken low (pc7). data appearing on the mosi output is valid on the falling edge of sck. serial data from the mc68hc11 is transmitted in 8-bit bytes with only 8 falling clock edges occurring in the transmit cycle. data is transmitted msb first. pc7 is taken high at the end of the write. 03161-043 mosi ad5425 1 sclk pc7 sdin sck mc68hc11 1 1 additional pins omitted for clarity. sync figure 43. 68hc11/68l11-to-ad5425 interface
ad5425 rev. a | page 21 of 28 microwire-to-ad5425 interface pic16c6x/7x-to-ad5425 figure 44 shows an interface between the dac and any microwire ? -compatible device. serial data is shifted out on the falling edge of the serial clock, sk, and is clocked into the dac input shift register on the rising edge of sk, which corresponds to the falling edge of the dacs sclk. the pic16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit (ckp) = 0. this is done by writing to the synchronous serial port control register (sspcon) (see the pic16/17 microcontroller user manual). in this example, i/o port ra1 is being used to provide a sync signal and enable the dac serial port. this microcontroller transfers eight bits of data during each serial transfer operation. figure 45 shows the connection diagram. 03161-044 cs ad5425 1 sclk sk sdin so microwire 1 1 additional pins omitted for clarity. sync 03161-045 ra1 ad5425 1 sclk sck/rc3 sdin sdi/rc4 pic16c6x/7x 1 1 additional pins omitted for clarity. sync figure 44. microwire-to-ad5425 interface figure 45. pic16c6x/7x-to-ad5425 interface
ad5425 rev. a | page 22 of 28 pcb layout and power supply decoupling in any circuit where accuracy is important, careful consider- ation of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5425 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the dac is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. these dacs should have an ample supply bypassing of 10 f in parallel with 0.1 f on the supply and located as close to the package as possibleideally up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), such as found in the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. low esr, 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and to filter out low frequency ripple. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. it is good practice to employ compact, minimum lead length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. to maximize high frequency performance, the i-to-v amplifier should be located as close to the device as possible. evaluation board the board consists of an 8-bit ad5425 and a current-to-voltage amplifier, the ad8065. included on the evaluation board is a 10 v reference, the adr01. an external reference can also be applied via an smb input. the evaluation kit consists of a cd-rom with self-installing pc software to control the dac. the software simply allows the user to write a code to the device. operating the evaluation board power supplies the board requires 12 v and 5 v supplies. the 12 v v dd and v ss are used to power the output amplifier, while the 5 v is used to power the dac (v dd1 ) and transceivers (v cc ). both supplies are decoupled to their respective ground plane with 10 f tantalum and 0.1 f ceramic capacitors. link1 (lk1) is provided to allow selection between the on- board reference (adr01) or an external reference applied through j2. link2 should be connected to the ldac position.
ad5425 rev. a | page 23 of 28 v dd p1?13 p1?5 p1?4 p1?2 p1?3 p1?19 p1?20 p1?21 p1?22 p1?23 p1?24 p1?25 p1?26 p1?27 p1?28 p1?29 p1?30 sclk sdin ldac sclk sclk sdin sync sdo gnd i out 2 v dd r fb v ref v dd1 v ref v dd +v in v out trim gnd i out 1 ad5425/ad5426/ ad5432/ad5443 u1 u3 c1 0.1 f p2?3 p2?2 p2?1 p2?4 agnd v ss v dd1 v dd c11 0.1 f c12 10 f c3 10 f c4 0.1 f c5 0.1 f c13 0.1 f c14 10 f c15 0.1 f c16 10 f + u2 adr01ar j2 c9 10 f c10 0.1 f r1 = 0 ad8065ar lk2 lk1 a b 7 6 5 4 1 3 9 10 8 sdin sync v ref tp1 sdo/ldac sdo/ldac sync c2 10 f + c5 4.7pf 3 6 2 7 4 2 v out j1 2 5 4 6 + c7 10 f c8 0.1 f v ss + j3 j4 j5 j6 + + 03161-046 v? v+ figure 46. schematic of the ad5425 evaluation board
ad5425 rev. a | page 24 of 28 03161-047 figure 47. component-side artwork eval?ad5425eb p1 p2 j2 j6 j5 j4 u1 u3 c11 u2 j3 vref vref j1 vout lk1 sdo/ldac sdo/ldac c10 c13 c14 c9 c1 r1 c2 c3 c6 c4 c16 c15 sync sync sdin sdin sclk sclk ldac lk2 sdo vdd vss vdd1 agnd tp1 c8 03161-048 figure 48. silkscreencomponent-side view (top layer)
ad5425 rev. a | page 25 of 28 03161-049 figure 49. solder-side artwork
ad5425 rev. a | page 26 of 28 table 11. overview of the ad54xx and ad55xx devices part no. resolution no. dacs inl (lsb) interface package features ad5424 8 1 0.25 parallel ru-16, cp-20 10 mhz bw, 17 ns cs pulse width ad5426 8 1 0.25 serial rm-10 10 mhz bw, 50 mhz serial ad5428 8 2 0.25 parallel ru-20 10 mhz bw, 17 ns cs pulse width ad5429 8 2 0.25 serial ru-10 10 mhz bw, 50 mhz serial ad5450 8 1 0.25 serial rj-8 10 mhz bw, 50 mhz serial ad5432 10 1 0.5 serial rm-10 10 mhz bw, 50 mhz serial ad5433 10 1 0.5 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5439 10 2 0.5 serial ru-16 10 mhz bw, 50 mhz serial ad5440 10 2 0.5 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5451 10 1 0.25 serial rj-8 10 mhz bw, 50 mhz serial ad5443 12 1 1 serial rm-10 10 mhz bw, 50 mhz serial ad5444 12 1 0.5 serial rm-8 10 mhz bw, 50 mhz serial interface ad5415 12 2 1 serial ru-24 10 mhz bw, 50 mhz serial ad5405 12 2 1 parallel cp-40 10 mhz bw, 17 ns cs pulse width ad5445 12 2 1 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5447 12 2 1 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5449 12 2 1 serial ru-16 10 mhz bw, 50 mhz serial ad5452 12 1 0.5 serial rj-8, rm-8 10 mhz bw, 50 mhz serial ad5446 14 1 1 serial rm-8 10 mhz bw, 50 mhz serial ad5453 14 1 2 serial uj-8, rm-8 10 mhz bw, 50 mhz serial ad5553 14 1 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5556 14 1 1 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5555 14 2 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5557 14 2 1 parallel ru-38 4 mhz bw, 20 ns wr pulse width ad5543 16 1 2 serial rm-8 4 mhz bw, 50 mhz serial clock ad5546 16 1 2 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5545 16 2 2 serial ru-16 4 mhz bw, 50 mhz serial clock ad5547 16 2 2 parallel ru-38 4 mhz bw, 20 ns wr pulse width
ad5425 rev. a | page 27 of 28 outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba figure 50. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model resolution (bits) inl (lsbs) temperature range package description branding package option ad5425yrm 8 0.25 ?40c to +125c msop d1p rm-10 ad5425yrm-reel 8 0.25 ?40c to +125c msop d1p rm-10 ad5425yrm-reel7 8 0.25 ?40c to +125c msop d1p rm-10 eval-ad5425eb evaluation kit
ad5425 rev. a | page 28 of 28 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03161-0-3/05(a)

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